1. Field of the Invention
The present invention generally relates to maintaining system time in a computer, More particularly, it relates to a modular implementation of a system dayclock which is capable of being partitioned amongst a number of bit slice modules.
2. Description of the Prior Art
A key element of general purpose data processing systems is the ability to maintain system time. In a typical system, the system time may be generated using a dayclock mechanism or equivalent. Dayclocks may be provided in either hardware or software, but are typically triggered off a pulsed signal having a regular period, such as the output of an oscillator.
The ability to maintain an accurate dayclock is important in many applications, and in particular high reliability real time data processing applications such as banking systems or airline reservations systems. In these applications, the dayclock may be used, inter alia, to time stamp data entries, thereby indicating the time sequence that the data entries are made. It can readily be seen that in an airline reservation application, the time sequence that airline reservations are made may be vitally important to the proper operation of the system. Similarly, the time that a particular banking transaction is made, relative to other transactions, may be important to maintain the integrity of the system.
One approach for generating a dayclock is suggested in U.S. Pat. No. 4,349,890 issued to Cheng. Cheng suggests generating a dayclock from the computer system clock. Cheng utilizes a counter circuit within a preselected number of bit positions to determine the elapsed time capacity and the resolution of the dayclock. Cheng relates the processor clock cycle to the time of day duty cycle, and thus, does not require reference to a time standard for checking the pulse source.
U.S. Pat. No. 4,708,491 issued to Luitje suggests using firmware to automatically adjust a time base used by the computer's dayclock. That is, Luitje suggests using a microcomputer with a timer system that is controlled by a crystal oscillator. All timing functions are related to a 16-bit free running counter where the counter is clocked by the output of the oscillator after the frequency of the oscillator is divided down by a prescaler circuit. The output of the prescaler circuit is measured to determine the frequency of the divided down clock, and this value is stored in an EEPROM to be used for computing a correction term between the effective frequency needed for the dayclock and the measured frequency. This approach, however, requires the use of a crystal oscillator to generate the correction term used for tuning the fundamental unit of time used to increment the counter.
Another approach uses a number of dayclock elements, wherein each dayclock element is directly connected to a central dayclock control element. Because each dayclock element must be directly connected to the central control element, this approach may require a substantial number of input/output pins and board routing channels. Further, this approach is essentially a singular design, and a separate control element may be required for each variation of the number and size of dayclock bit slices that make up a full dayclock.
It is often desirable and frequently necessary to provide multiple dayclocks. For example, multiple dayclocks may be necessary to allow multiple processors to exchange messages or access the same memory storage devices. An approach for implementing a number of dayclocks within a computer processing system is suggested in U.S. Pat. No. 5,146,585 issued to Smith. Smith suggests a fault tolerance synchronization mechanism consisting of dual redundant dayclock synchronization sources in a number of dayclock slave elements. Each of the dayclock slave elements serve as dayclocks in a number of corresponding processors within a system. Here, the redundant dayclock sources distribute a time of day synchronization signal to each of the dayclock slave elements. To achieve better conformity to real time, Smith suggests correcting the generator reference signal by summing predetermined numbers of cycles of the signal and comparing the result to a more precise time standard.
A limitation of all of the above prior art approaches is that a substantial amount of hardware is required in the implementation thereof, including a substantial amount of input/output pins and board route channels. This is particularly problematic when high density integrated circuits are employed where the number of input and output pins is limited relative to the amount of logic elements provided. Further, the above prior art schemes emphasis singular design approaches, rather than a modular approach wherein dayclock elements may be combined as necessary to accommodate various bit slice arrangements.